The India semiconductor manufacturing fund has moved from policy document to construction site. In the 2026-27 Union Budget, the government allocated Rs. 8,000 crore, its largest single-year semiconductor outlay since the mission launched, as part of the India Semiconductor Mission (ISM) 2.0 framework. That annual figure sits within a broader total incentive pool that, when combined with ISM 1.0 investments and the Design Linked Incentive scheme, produces a headline commitment in the $10.8 billion range. What does that actually fund, and why are NRI engineers in Austin and Santa Clara paying attention?
The infrastructure milestone came on February 28, 2026, when Prime Minister Modi inaugurated Micron Technology’s Assembly, Test, Marking, and Packaging facility in Sanand, Gujarat. This $2.75 billion plant, India’s first operational semiconductor facility of the current mission cycle, is projected to ship at nearly 6.3 million chips per day. The Micron facility focuses on advanced packaging of DRAM and NAND flash memory, a critical bottleneck for AI server supply chains.
What Exactly Is Being Built at Dholera?
The centrepiece of the entire program is the Tata Electronics and Powerchip Semiconductor Manufacturing Corporation joint facility in the Dholera silicon hub. Located in the Dholera Special Investment Region in Gujarat, which received SEZ status in April 2026, the fab covers 66 hectares and is designed to produce 50,000 wafer starts per month at 28nm to 110nm process nodes. The total investment is approximately Rs. 91,000 crore, with the central government providing 50% of capex on a pari-passu basis. First silicon, meaning the first commercially viable wafers produced on the production line, is targeted for December 2026 per Union Minister Ashwini Vaishnaw’s confirmed timeline.
These process nodes, 28nm, 40nm, 55nm, 90nm, are not the bleeding-edge sub-5nm nodes used in flagship smartphones. They are the workhorse nodes powering automotive chips, display drivers, power management ICs, industrial microcontrollers, and IoT devices. These are the categories experiencing the most acute global supply shortfalls, and India is targeting them precisely.
Key Facilities Under India Semiconductor Mission 2.0
| Facility | Location | Type | Status |
| Tata-PSMC Fab | Dholera, Gujarat | Front-end wafer fab (28-110nm) | First silicon: Dec 2026 |
| Micron ATMP | Sanand, Gujarat | Memory packaging | Operational (Feb 2026) |
| CG Power ATMP | Sanand, Gujarat | Assembly and test | Scaling production 2026 |
What Is DLI 2.0 and Why Does It Matter for Startups?
The Design Linked Incentive DLI 2.0 program represents a separate strategic track within the broader mission. As of May 2026, the DLI scheme has provided design infrastructure support to 315 academic institutions and 104 startups. The 24 semiconductor design startups currently supported under the program have attracted Rs. 430 crore in venture capital funding. Qualcomm has already executed a 2nm tape-out from Indian design centres, a signal that the design ecosystem is credible enough for tier-one semiconductor companies to use for leading-edge work.
The $500 million DLI 2.0 allocation specifically targets high-gestation design ventures that need patient capital rather than return-driven investment timelines. For fabless chip design startups working on AI accelerators, satellite communication chips, and energy metering ICs, these are the economic conditions that make India viable as a design hub rather than just a cost-reduction destination.
The Reverse Brain Drain Story: Why NRI Engineers Are Looking at This Seriously
The reverse brain drain tech corridor narrative has been a perennial promise in India-US policy conversations. This time, the fundamentals are different. The US-China technology decoupling has created genuine demand for non-China, non-Taiwan semiconductor capacity. TSMC in Arizona, Samsung in Texas, and Intel’s foundry expansion are absorbing some of that demand but cannot meet it alone. India, with English-language engineering talent, a non-China geopolitical alignment, and active government subsidies, is being evaluated by NRI engineers in ways that were not economically realistic even two years ago.
The Micron facility in Sanand has already recruited senior process engineers from both TSMC alumni networks and former Intel employees. The Tata-PSMC fab is actively recruiting process integration and yield engineers, roles that command Rs. 60 to 100 lakh annually in India versus $200,000 to $300,000 equivalent in Austin or Santa Clara. The salary arbitrage is narrowing, and the equity upside in early-stage Indian semiconductor ventures is becoming a legitimate career consideration. For NRI professionals tracking these opportunities, the science and technology section of The Indian Panorama provides ongoing coverage.
The Geopolitical Tailwind
The timing of the $10.8 billion commitment is not coincidental. The 2026 Iran war and the resulting Strait of Hormuz shipping crisis have underscored the fragility of centralized hardware production in conflict-adjacent geographies. Supply chains that run through volatile maritime corridors are being repriced for risk by every major technology company. India’s west coast industrial position, specifically the Dholera SIR, offers a supply chain profile that is geographically diversified from both Taiwan Strait risk and Middle East risk.
For the Indian diaspora watching this story, the semiconductor push is not just an industrial policy item. It is a potential generational economic reshaping of what career paths look like for the next cohort of NRI engineers deciding whether to stay in Silicon Valley or return to a valley of a different kind. To connect with The Indian Panorama editorial team on this story, visit our contact page.
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